Digital subscriber lines (DSL) provide the key technologies in our days and help to improve the speed of communications networks. DSL offers extremely fast data transfer on existing copper-based telephone lines. In DSL, broad-band data signals are transmitted on significantly higher frequencies than the traditional narrow-band telephone signals. Since both types of signals, the narrow-band telephone signals and the broad-band data signals, are transmitted over the same subscriber line, splitter devices are provided for splitting and recombining the two types of signals at both ends of the subscriber line: first at the central office or switching center, and second at the end terminals at the subscriber location.
FIG. 1 shows schematically the topology of such an telephone network coexisting with a data overlay network.
A central office CO is coupled over the subscriber lines SL1, SL2, . . . SLN to the subscribers S1, S2, . . . SN, wherein at each location splitter devices SPO, SP1, SP2, . . . SPN are provided for separating and combining the DSL broad-band and telephone narrow-band signals.
The signals generated at the central office CO and at the subscriber locations have to fulfill certain requirements. An exemplary standard for “asymmetric digital subscriber line (ADSL) transceivers provides the ITU-T Recommendation G.992.1 (06/99), series G: Transmission systems and media, digital systems and networks.
A common line code for transmitting digital data on the asymmetric digital subscriber line is provided by discrete multitone modulation (DMT). In DMT, a given frequency range for data transmission is resolved into a number of narrow-frequency bands for use as individual data links. In ADSL, data transmission occurs roughly between 20 kHz and 1 MHz.
The power spectral density (PSD) of a line code defines the distribution of the line codes power in the frequency domain. Because the frequencies used in the DSL standard must not interfere with other applications in the same frequency band, e.g. radio transmission, so-called PSD masks are introduced. A PSD mask is a template that specifies the maximum PSD allowable for a line code. PSD masks are used as guidelines for the design and implementation of a DSL technology.
FIG. 2 shows a transmit PSD mask according to the ITU-T G992.1 recommended ADSL standard.
The transmit ADSL PSD mask is piecewise continuous and requires −97.5 dBm/Hz up to 4 kHz with a maximum power in the 0-4 kHz band of 15 dB, a slope of 21 dB/octave between 4 (corresponding to −92.5 dB/Hz peak requirement) and 24.875 kHz (correponding to −36.5 dB/Hz peak requirement), −36.5 dBm/Hz between 25.875 and 1104 kHz, a negative slope of −36 dB/oct between 1104 and 3093 kHz and −90 dBm/Hz above 3093 kHz as a peak requirement (PR). Certain standards even require that the power spectral density is below −110 dBm/Hz above 4545 kHz.
Further, the maximum power in any 1 MHz wide sliding frequency window above 4545 kHz must be below −50 dBm, and the maximum transmitted total power must not be more than 19.8 dBm between 25.875 kHz and 1104 kHz.
In order to transmit the ADSL data signals over the telephone line that consists of a pair of copper wires—also named as subscriber loop or twisted pair line—the central office must be provided with line drivers. The line drivers compensate for the attenuation of lines and they have to comply with the PSD mask requirements. A line driver has to amplify the line-coded ADSL signal in a way that it is received downstream at the subscriber locations with a sufficient intensity. Similarly, line drivers should be provided at the subscriber locations for transmitting ADSL data upstream to the central office. Both line drivers need to comply with similar requirements with respect to the PSD masks given by the relevant standards.
A basic component of a line driver is a power amplifier for amplifying the DSL signal which is to be transmitted over the telephone line.
Traditionally, linear class-AB amplifiers were used. However, driving transistors in a class-AB amplifier are biased to operate in their linear region which results in that they are always in an on-state and draw precious quiescent current. This results in an inefficient power dissipation. For example, a state-of-the-art class-B line driver consumes 750 mW when transmitting 100 mW which is a power efficiency of only 13%.
The way to improve the power efficiency of a power amplifier is to operate the output transistors as switches. These amplifiers are also called class D-amplifiers. When a transistor is switched off the current through is approximately zero. When the transistor switched on, the voltage across the transistor is small, ideally zero. In each case the power dissipation is very low. This increases efficiency thus requiring less power from the power supply and smaller heat sinks for the amplifier. These are important advantages in portable battery powered equipment.
FIG. 3 shows a line driver including a class D-power amplifier according to the state of the art. Such a line driver includes a class D-power amplifier and a demodulation filter connected in series.
FIG. 4 shows a schematic of such a conventional class-D amplifier in principle.
The class-D amplifier as shown in FIG. 4 comprises a comparator CP for receiving a triangle wave signal T providing a switching frequency (fS), that is generated by a triangle wave generator TG, and an input signal S1. The comparator CP compares the triangle wave signal T with the input signal S1 to create a variable duty cycle square wave signal S2. In effect, a pulse train is created with a duty cycle proportional to the input signal S1 level. This pulse width modulated signal S2 is coupled via a phase control circuit to gates of complementary output transistors P, N wherein their respective source drain paths are connected in series between a supply voltage VDD and ground GND. The amplified output signal S3 is tapped at a node between the source drain paths.
In effect, the pulse width modulated (PWM) signal with a duty cycle proportional to the input signal level turns the complementary output transistors P, N on and off at a switching frequency (fS) that is much greater than the highest frequency of the input signal S1. Hence, power is sufficiently delivered from the power supply to the load.
The efficiency of the class D-amplifier as shown in FIG. 4 is high because there is little voltage drop across the switch transistors P, N during conduction. These means a very low power dissipation in the switches while virtually all the power is transferred to the load connected to the output of the class D-power amplifier. The phase control circuit receives the pulse width modulated output signal S2 of the comparator and delays signals such that the two complementary power MOSFETs P, N are not switched through at the same time. Class D-power amplifiers can reach an efficiency as high as 90%.
FIG. 5 shows a signal time diagram of the signals within a conventional class D-power amplifier as shown in FIG. 4. The comparator compares the supplied analog input signal S1 which is in the given example an analog sine wave signal. These signal is compared to a triangular signal T generated by the triangle wave generator. If the amplitude of the sine wave signal is higher than the triangular signal T a comparator supplies a low output signal to the driving stage formed by the complementary MOSFETs whereas when the amplitude of the triangular signal is higher than the applied input signal the output of the comparator CP is high. Accordingly the signal S2 supplied to the driving stage is a pulse width modulated signal PWM representing the applied input signal S1. The driving stage does not amplify the original analog input signal S1 but the digital representation, i.e. the pulse width modulated signal S2 such increasing power efficiency. As can be seen in FIG. 4 the comparator CP and the driving stage are supplied with the same supply voltage VDD.
A further disadvantage of the class D-power amplifier as shown in FIG. 4 is that when integrated on a CMOS single chip the maximum supply voltage VDD is 3V so that the maximum voltage swing on the output of the class D-power amplifier is lower than 3V.
A further draw back of the class D-power amplifier as shown in FIG. 4 is that a triangle wave generator is necessary to generate the triangle wave signal T used by the comparator CP. The triangle wave generator is relative complex in structure and needs a lot of chip area when integrating a class D-power amplifier on a chip.